Soft Mixed Signal Corporation USB 2.0 PHY IP Cores
USB 2.0 PHY Verification
USB v2.0 Soft PHY and Device Controller
TUSB1210 data sheet, product information and support | TI.com
HSIC USB 2.0 PHY IP
USB 2.0 Full High Speed Solution | NXP Semiconductors
USB3250 | Microchip Technology
Mixed-Signal Verification for USB 2.0 Physical Layer IP
USB 3.0/2.0 Combo PHY IP for SoC Designs | Cadence IP
TUSB1210-Q1 data sheet, product information and support | TI.com
USB 2.0 PHY IP Core Device Host OTG Hub in TSMC, 28HPC, 40LP /LL, UMC, 40LP, 28HPC, SMIC 14SF, SF, 55LL, 40LL - T2M-IP
USB2 Controller | Cadence
DWTB: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
The USB 2.0 Device IP core | Arasan Chip Systems
高速USB 2.0 phy-Mentor图形- 188金宝搏
USB2.0 Soft IP: An Introduction to GOWIN Semiconductor's USB Solution for FPGA's - YouTube
USB 2.0 Full High Speed Solution | NXP Semiconductors
USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 40LP /LL)
USB 2.0 extender control chipCH317 - NanjingQinhengMicroelectronics
XPS USB 2.0 Host Controller
Figure 1 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
The Next-Generation Interconnect | Mouser
